AMD EPYC 7252 Server Processor
Procurement readiness
RFQ ReadyThe catalog record is approved for a standard quote request; current commercial terms still require RFQ review.
AMD EPYC 7252 is an 8-core, 16-thread EPYC 7002 Series processor with 64 MB L3 for single- or dual-socket SP3 server platforms. It has a 3.1 GHz base clock and 120 W default TDP.
Quick Facts
- Cores
- 8
- Threads
- 16
- Base clock
- 3.1 GHz
- Default TDP
- 120 W
Highlights
- 8 cores / 16 threads with 64 MB L3
- 1P / 2P socket configuration; 120 W default TDP
- 85.3 GB/s theoretical per-socket bandwidth; population conditions apply
- PCIe 4.0 x128 per CPU; platform-dependent system lanes
Source-backed product identity
RFQ before payment
Order terms confirmed in quotation
Exact availability, condition, warranty, lead time and shipping scope are confirmed in the quotation.
Technical Specifications
Platform & Compute
The 8-core 7252 combines 64 MB L3 and a 120 W default TDP with 1P / 2P capability. It has the reduced 85.3 GB/s per-socket memory-bandwidth specification, unlike the 8-core 7262. An SP3 socket does not establish motherboard or server compatibility. Check the exact OEM supported CPU list, BIOS, memory population, power and cooling. First-generation EPYC motherboards require OEM BIOS updates; AMD identifies 7742, 7642 and 7542 as requiring additional updates. PCIe 4.0 and DDR4-3200 support need OEM confirmation, and a second-generation EPYC motherboard is required for all available functionality.
Platform & Compute
The 8-core 7252 combines 64 MB L3 and a 120 W default TDP with 1P / 2P capability. It has the reduced 85.3 GB/s per-socket memory-bandwidth specification, unlike the 8-core 7262. An SP3 socket does not establish motherboard or server compatibility. Check the exact OEM supported CPU list, BIOS, memory population, power and cooling. First-generation EPYC motherboards require OEM BIOS updates; AMD identifies 7742, 7642 and 7542 as requiring additional updates. PCIe 4.0 and DDR4-3200 support need OEM confirmation, and a second-generation EPYC motherboard is required for all available functionality.
| Model | EPYC 7252 |
|---|---|
| Architecture | Zen 2 |
| Series | EPYC 7002 |
| Socket | SP3 |
| Socket count | 1P / 2P |
| Cores | 8 |
| Threads | 16 |
Performance & Capacity
Maximum boost is a single-core maximum under normal server operating conditions, not a sustained or all-core frequency guarantee.
Performance & Capacity
Maximum boost is a single-core maximum under normal server operating conditions, not a sustained or all-core frequency guarantee.
| Base clock | 3.1 GHz |
|---|---|
| Maximum boost | Up to 3.2 GHz (single-core maximum; operating conditions apply) |
| All-core boost | Unknown |
| L3 capacity | 64 MB |
Memory
Up to DDR4-3200 means 3200 MT/s at one DIMM per channel (1DPC). Actual speed depends on DIMM type, population, BIOS and the supported OEM configuration. The 85.3 GB/s per-socket bandwidth is theoretical, not measured application throughput. Eight memory channels are supported, but this model is performance-optimized for four channels with DDR4-2667 DIMMs. Additional memory channels will not increase overall memory bandwidth. AMD’s 7002 technical guides specify up to 4 TB per processor as a series-level ceiling, with eight channels and up to two DIMMs per channel. This is not a guarantee for every OEM platform, DIMM population, or speed/capacity combination.
Memory
Up to DDR4-3200 means 3200 MT/s at one DIMM per channel (1DPC). Actual speed depends on DIMM type, population, BIOS and the supported OEM configuration. The 85.3 GB/s per-socket bandwidth is theoretical, not measured application throughput. Eight memory channels are supported, but this model is performance-optimized for four channels with DDR4-2667 DIMMs. Additional memory channels will not increase overall memory bandwidth. AMD’s 7002 technical guides specify up to 4 TB per processor as a series-level ceiling, with eight channels and up to two DIMMs per channel. This is not a guarantee for every OEM platform, DIMM population, or speed/capacity combination.
| Memory type | DDR4 |
|---|---|
| Supported channels | 8 |
| Transfer rate | Up to 3200 MT/s at one DIMM per channel (1DPC); OEM configuration applies |
| Theoretical bandwidth per socket | 85.3 GB/s |
| Maximum capacity | Up to 4 TB per CPU (series-level ceiling; DIMM/OEM conditions apply) |
| Population optimization | 4 channels with DDR4-2667 DIMMs; additional channels do not increase overall bandwidth |
Expansion
PCIe 4.0 x128 per CPU. Available system lanes depend on platform routing, storage connections and processor interconnect; a dual-socket system lane count is not a per-CPU specification.
Expansion
PCIe 4.0 x128 per CPU. Available system lanes depend on platform routing, storage connections and processor interconnect; a dual-socket system lane count is not a per-CPU specification.
| PCIe generation | PCIe 4.0 |
|---|---|
| Lanes per CPU | 128 |
Power & Cooling
The selected OEM server must support EPYC 7252 and its 120 W default power and cooling requirements. No universal SP3 platform compatibility is implied.
Power & Cooling
The selected OEM server must support EPYC 7252 and its 120 W default power and cooling requirements. No universal SP3 platform compatibility is implied.
| Default TDP | 120 W |
|---|---|
| Configurable TDP | Unknown; complete range not established |
Lifecycle
Exact model launch date is Unknown. Historical family or model announcements are separate events and do not establish current manufacturing, end-of-life, end-of-sale, inventory or regional availability. Current lifecycle is Unknown. AMD announced the second-generation EPYC family on 2019-08-07. This family event is not assigned as this model’s exact launch date.
Lifecycle
Exact model launch date is Unknown. Historical family or model announcements are separate events and do not establish current manufacturing, end-of-life, end-of-sale, inventory or regional availability. Current lifecycle is Unknown. AMD announced the second-generation EPYC family on 2019-08-07. This family event is not assigned as this model’s exact launch date.
| Exact model launch date | Unknown |
|---|---|
| Current manufacturing | Unknown |
| End of life | Unknown |
| End of sale | Unknown |
Procurement Identity
Use the base model and listed identifiers when building a multi-model RFQ. The selected PID, destination, configuration and commercial terms are confirmed before a quote is issued.
- Orderable part number
- 100-000000080
- Orderable PID options
- 100-000000080, 100-100000080WOF
- Lifecycle / commercial status
- Unknown
- Quote inputs
- PID or base model, quantity, destination and required configuration
Technical Documents
FAQ
Which ordering identifiers identify EPYC 7252?
AMD lists tray OPN 100-000000080 and boxed OPN 100-100000080WOF for the same EPYC 7252. These are packaging ordering variants, not separate processor models. Requested packaging and package contents require confirmation; neither identifier establishes present supply.
What distinguishes EPYC 7252 during platform selection?
The 8-core 7252 combines 64 MB L3 and a 120 W default TDP with 1P / 2P capability. It has the reduced 85.3 GB/s per-socket memory-bandwidth specification, unlike the 8-core 7262. An SP3 socket does not establish motherboard or server compatibility. Check the exact OEM supported CPU list, BIOS, memory population, power and cooling. First-generation EPYC motherboards require OEM BIOS updates; AMD identifies 7742, 7642 and 7542 as requiring additional updates. PCIe 4.0 and DDR4-3200 support need OEM confirmation, and a second-generation EPYC motherboard is required for all available functionality.
What memory limits and population conditions apply to EPYC 7252?
Up to DDR4-3200 means 3200 MT/s at one DIMM per channel (1DPC). Actual speed depends on DIMM type, population, BIOS and the supported OEM configuration. The 85.3 GB/s per-socket bandwidth is theoretical, not measured application throughput. Eight memory channels are supported, but this model is performance-optimized for four channels with DDR4-2667 DIMMs. Additional memory channels will not increase overall memory bandwidth. AMD’s 7002 technical guides specify up to 4 TB per processor as a series-level ceiling, with eight channels and up to two DIMMs per channel. This is not a guarantee for every OEM platform, DIMM population, or speed/capacity combination.
Is maximum boost guaranteed across all cores?
Maximum boost is a single-core maximum under normal server operating conditions, not a sustained or all-core frequency guarantee.
Do historical announcements establish current availability?
Exact model launch date is Unknown. Historical family or model announcements are separate events and do not establish current manufacturing, end-of-life, end-of-sale, inventory or regional availability. Current lifecycle is Unknown. AMD announced the second-generation EPYC family on 2019-08-07. This family event is not assigned as this model’s exact launch date.
RFQ
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Brand
AMD
Model
EPYC 7252
Product family
EPYC 7002 Series
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